High-Speed Impedance: USB, HDMI, PCIe
Complete reference guide for high-speed interface impedance requirements. Covers USB 2.0/3.0, HDMI, PCIe Gen 1-5, DDR3/4/5, and more with practical design tips.
Every high-speed interface—USB, HDMI, PCIe, DDR—has specific impedance requirements. Get them wrong, and you'll face signal integrity issues, failed compliance testing, or devices that simply don't work. This guide summarizes nominal impedance targets; confirm the requirements for your interface and device before routing.
Tolerance, skew and loss budgets: see the current interface specification and your device datasheet; this article does not state them.
USB Impedance Requirements
USB is everywhere, but each generation has different impedance and routing requirements. USB 2.0/3.x use a nominal 90Ω differential target; USB4 uses a nominal 85Ω target.
| USB Version | Data Rate | Nominal Diff. Impedance |
|---|---|---|
| USB 2.0 FS | 12 Mbps | 90Ω nominal |
| USB 2.0 HS | 480 Mbps | 90Ω nominal |
| USB 3.0 (3.2 Gen1) | 5 Gbps | 90Ω nominal |
| USB 3.1 (3.2 Gen2) | 10 Gbps | 90Ω nominal |
| USB 3.2 Gen2×2 | 20 Gbps | 90Ω nominal |
| USB4 | 40/80 Gbps | 85Ω nominal |
USB 3.0+ Routing Tips:
- Set TX and RX pair separation using the device routing guidance
- Use ground via stitching between pairs
- Avoid layer transitions if possible
- Match lengths within each differential pair
HDMI Impedance Requirements
For HDMI TMDS (Transition Minimized Differential Signaling) routing, check the data and clock requirements in the current interface specification and your device datasheet.
| HDMI Version | Max Data Rate | Nominal Diff. Impedance |
|---|---|---|
| HDMI 1.4 | 10.2 Gbps | 100Ω nominal |
| HDMI 2.0 | 18 Gbps | 100Ω nominal |
| HDMI 2.1 | 48 Gbps | 100Ω nominal |
HDMI Routing Guidelines
- TMDS pairs: Route as tightly coupled differential pairs
- Clock: Follow the device timing and length-matching requirements
- DDC (I²C): Can be routed as standard traces, not impedance-controlled
- CEC: Single-ended, not critical for routing
- HPD: Single-ended, not critical for routing
PCI Express (PCIe) Impedance Requirements
PCIe data rates increase with each generation. Check the channel requirements for your generation and device when planning impedance control and routing.
| PCIe Gen | Data Rate | Nominal Diff. Impedance |
|---|---|---|
| PCIe 1.0 | 2.5 GT/s | 85Ω nominal |
| PCIe 2.0 | 5 GT/s | 85Ω nominal |
| PCIe 3.0 | 8 GT/s | 85Ω nominal |
| PCIe 4.0 | 16 GT/s | 85Ω nominal |
| PCIe 5.0 | 32 GT/s | 85Ω nominal |
| PCIe 6.0 | 64 GT/s | 85Ω nominal |
PCIe Gen4+ Routing Considerations:
- Evaluate the routing structure using your stackup and channel requirements
- Minimize via transitions and evaluate their effect on the channel
- Control impedance at via transitions
- Consider back-drilling for stub reduction
- Evaluate dielectric loss when selecting materials for Gen5+
DDR Memory Impedance Requirements
DDR memory uses a combination of single-ended and differential signals. The data/address lines are single-ended, while the clock and strobes are differential.
| DDR Gen | Data Rate | Nominal Signal Z₀ | Nominal Clock Zdiff |
|---|---|---|---|
| DDR3 | 800-2133 MT/s | 40Ω nominal | 80Ω nominal |
| DDR4 | 1600-3200 MT/s | 40Ω nominal | 80Ω nominal |
| DDR5 | 4800-8400 MT/s | 40Ω nominal | 80Ω nominal |
| LPDDR4 | 3200-4266 MT/s | See device datasheet | See device datasheet |
| LPDDR5 | 6400-8533 MT/s | 40Ω nominal | 80Ω nominal |
DDR Length Matching
Use the memory controller and memory device documentation to define matching groups and timing constraints for data, strobes, address/command, clock, and control signals.
Ethernet Impedance Requirements
Ethernet signaling has evolved significantly, with 10GBASE-T and beyond requiring precise impedance control.
| Standard | Data Rate | Impedance |
|---|---|---|
| 10/100BASE-TX | 10/100 Mbps | 100Ω nominal |
| 1000BASE-T | 1 Gbps | 100Ω nominal |
| 2.5GBASE-T | 2.5 Gbps | 100Ω nominal |
| 5GBASE-T | 5 Gbps | 100Ω nominal |
| 10GBASE-T | 10 Gbps | 100Ω nominal |
Note: The traces between the PHY and magnetics transformer are the a section to review against the PHY and magnetics documentation; also check the cable-side layout requirements.
SATA and SAS Impedance
| Interface | Data Rate | Diff. Impedance |
|---|---|---|
| SATA I | 1.5 Gbps | See specification and device datasheet |
| SATA II | 3 Gbps | See specification and device datasheet |
| SATA III | 6 Gbps | See specification and device datasheet |
| SAS-1 | 3 Gbps | See specification and device datasheet |
| SAS-2 | 6 Gbps | See specification and device datasheet |
| SAS-3 | 12 Gbps | See specification and device datasheet |
Display Interfaces (DisplayPort, MIPI)
| Interface | Data Rate | Impedance | Type |
|---|---|---|---|
| DisplayPort 1.4 | 8.1 Gbps/lane | See specification and device datasheet | Differential |
| DisplayPort 2.0 | 20 Gbps/lane | See specification and device datasheet | Differential |
| MIPI DSI | 1.5 Gbps/lane | See specification and device datasheet | Differential |
| MIPI CSI-2 | 2.5 Gbps/lane | See specification and device datasheet | Differential |
| LVDS | 655 Mbps | 100Ω nominal | Differential |
| eDP | 8.1 Gbps/lane | See specification and device datasheet | Differential |
Quick Reference: All Interfaces
| Interface | Diff Z | SE Z |
|---|---|---|
| USB 2.0/3.x | 90Ω nominal | See device datasheet |
| USB4 | 85Ω nominal | See device datasheet |
| HDMI | 100Ω nominal | See device datasheet |
| PCIe | 85Ω nominal | See device datasheet |
| DDR | 80Ω nominal | 40Ω nominal |
| Ethernet | 100Ω nominal | See device datasheet |
| SATA | See specification and device datasheet | See device datasheet |
| DisplayPort | See specification and device datasheet | See device datasheet |
| MIPI | See specification and device datasheet | See device datasheet |
General High-Speed Design Guidelines
1. Reference Plane Integrity
Every high-speed trace needs a continuous reference plane. Splits, voids, and gaps in the reference plane cause impedance discontinuities and return path problems.
2. Via Transitions
Each layer transition adds capacitance and inductance. Minimize transitions for high-speed signals. When transitions are needed, use ground vias nearby. See our Signal Via Guide.
3. Differential Pair Coupling
Keep differential pairs tightly coupled throughout their length. Maintain consistent spacing. Avoid routing between the traces of a pair.
4. Length Matching
Follow the device routing guidance when adding length-matching structures, and evaluate their effect on signal integrity.
Calculate Your Trace Dimensions
Now that you know your target impedance, use our calculators to determine the right trace dimensions:
Related Reading
Related Tools & Resources
USB Trace Calculator
USB 2.0/3.0/4.0 differential pair design
HDMI Impedance Calculator
HDMI 1.4/2.0/2.1 high-speed design
PCIe Impedance Calculator
PCIe Gen 3/4/5/6 high-speed design
DDR4/DDR5 Routing Calculator
Memory interface routing and timing
Ethernet Trace Calculator
10/100/1G/10G Ethernet routing
LVDS Trace Calculator
Low-voltage differential signaling design
Related Articles
Ready to Calculate?
Put your knowledge into practice with our free PCB design calculators.