Via Sizing: How Many Vias Needed?

Before calculating via count, it helps to understand what determines a via's current and thermal capacity.

Illustrative dimensions only, not fabrication limits from a standard. Confirm finished-hole, annular-ring, and aspect-ratio limits with the fabricator.

The current capacity of a single via depends on plating thickness, drill size, and allowable temperature rise.

Calculation basis: the legacy “drill” labels in the electrical tables mean finished inner diameter d, as in the calculator. With plating p, A = πp(d+p); for a pre-plating drill D use d = D − 2p, so A = πp(D−p). All electrical tables use p = 1 mil (25.4 μm). The site uses I = 0.048 × ΔT^0.44 × A^0.725 (A in mil²), an IPC-2221-style approximation, not a measured via rating or a thermal simulation. Displayed values are rounded.

There are two practical ways to size a via array depending on whether you care most about current delivery or matching the connected copper geometry.

Round up only after applying the selected factor: N = ceil(I × F / I_via). The factors 1.25 and 1.5 are illustrative rules of thumb, not requirements from a standard or guarantees of reliability. Area matching is a separate geometric check; it does not establish equal thermal performance. Counts use unrounded areas and currents; 1oz trace copper = 1.37 mil.

For fast estimates, this table assumes 10 mil drill vias with 1 mil plating and 10°C temperature rise.

Columns use F = 1, 1.25, and 1.5 respectively, with ideal equal current sharing. “Recommended” and “High-Rel” are illustrative margins, not certified ratings. Check copper connections, plating tolerance, and thermal coupling.

Different via arrays are optimized for different jobs. A power transition array is not the same as a thermal pad array or a stitching fence.

Power counts are calculated examples, not application requirements: use N = ceil(I × 1.25 / I_via), 1 mil plating and 10°C rise. Each range uses the smallest listed finished hole for both current endpoints. The thermal table is a rule of thumb, not from a standard: watts and pad area alone cannot determine a safe via count. Validate against the device land pattern, board stackup, and thermal analysis.

Ground stitching keeps return paths short and predictable for high-speed signals. Spacing depends on the highest frequency you care about.

Rule of thumb, not from a standard: λ ≈ c/(f√ε_eff), with c ≈ 300 mm/ns and assumed ε_eff = 4. The table uses spacing λ/20. Actual FR4 and field geometry vary; signal edge harmonics and local return transitions can require closer vias, even at 100 MHz.

Placement dimensions here are illustrative rules of thumb, not minima from a standard. Fabricator clearance rules, land patterns, solder assembly, and return-path analysis take precedence.

Vias add resistance as well as temperature rise. In low-voltage rails, that resistance can matter almost as much as heating.

Resistance follows the production via model: R = ρL/A, L = 62 mil, ΔT = 10°C, and ρ = 1.724 × 10⁻⁸ × [1 + 0.00393 × (ΔT/2)] Ω·m. Its assumed average copper temperature is 25°C. The 1A voltage drop is I × R; it is not a thermal solve at 1A.

These are illustrative design examples, not measured boards. The motor count uses the full 8A as a steady-current sizing input; pulse duration is not modeled. The thermal and signal layouts are rules of thumb, not from a standard, and do not prove thermal or signal compliance. For exposed pads, follow the device-specific land pattern and assembly guidance in TI PowerPAD, SLMA002H.

Current estimates are not guaranteed safe ratings. Confirm minimum finished plating, fabrication rules, and actual temperatures.

This is a good first-pass shortcut for 10 mil vias with 1 mil plating at a 10°C rise.

For model estimates using your dimensions, use the Via Current Calculator. It accounts for via size, plating thickness, board thickness, and temperature rise.

N = ceil(I × 1.25 / I_via), with I_via ≈ 1.7246 A for a 10 mil finished hole, 1 mil plating and 10°C rise. Use the unrounded calculator result near integer boundaries. The model scales parallel capacity linearly and resistance as 1/N; it does not model unequal sharing or thermal coupling. Board thickness affects resistance, not the capacity power law.