Focused Power Electronics Use Pattern

MOSFET Gate Driver PCB Layout Calculator

Gate Loop | Bootstrap Layout | Half-Bridge Placement

Use this page to choose a defensible starting point for MOSFET gate driver PCB layout: gate trace width, resistor placement, gate-return routing, and the practical conditions that decide whether your half-bridge or synchronous power stage switches cleanly or rings itself into trouble.

Quick Answer

Treat MOSFET gate driver layout as a loop-inductance problem before you treat it as a trace-width problem. Put the driver close to the MOSFETs, keep the gate and gate-return path compact and symmetric, place the gate resistor at the MOSFET gate pin, keep the bootstrap loop tight, and only widen the gate trace after the placement and return path are already correct. On most FR4 boards, a short 10 to 20 mil gate trace is a workable starting range, but loop area, via count, and Kelvin-source discipline dominate switching behavior.

Key Takeaways

-The main failure mode is usually excess gate-loop inductance, not a gate trace that is one or two mil too narrow.
-Place the gate resistor at the MOSFET gate, not back at the driver, so the resistor damps the actual high-dI/dt loop.
-Use a dedicated gate return or Kelvin source path whenever the source lead also carries large power current.
-Every via in the gate loop adds inductance; if the gate must change layers, move the full gate-and-return path together and keep it short.

Use The Right Tool In Sequence

Gate-drive routing gets better when you separate jobs correctly: size the high-current copper with the trace width calculator, verify layer transitions with the via current calculator, and lock the real laminate and spacing assumptions with the FR4 calculator.

Power Path

Trace Width Calculator

Size bus, phase, shunt, and driver-supply copper separately from the gate loop.

Transitions

Via Current Calculator

Check bottlenecks where gate-return or driver-supply paths must change layers.

Context

Motor Driver Copper Guide

Review the surrounding half-bridge layout so the gate loop lives inside a sane power stage.

MOSFET Gate Driver Layout Decision Matrix

Use Pattern	Switching Regime	Dominant Constraint	Starting Geometry	Recommendation
24 V to 48 V synchronous buck	100 kHz to 500 kHz	Bootstrap loop and switch-node coupling	10 to 15 mil short gate traces	Keep high-side bootstrap parts at the driver pins and shield the gate loop from the switch node.
BLDC or servo half-bridge	10 kHz to 100 kHz PWM	Shared source inductance and current-sense noise	12 to 20 mil with dedicated return path	Prioritize Kelvin source routing and keep the driver inside the power stage rather than near the MCU.
High-current low-voltage bridge	Fast edges, large peak gate current	Package lead inductance and via bottlenecks	Wide, short gate path with minimal layer changes	Avoid neck-downs around pads and check every driver-to-FET transition, not only the visible straight section.
Fast silicon or GaN power stage	Sub-10 ns class edges	Parasitic inductance and coupling control	Driver-specific layout from vendor notes	At this point, component placement, return-path adjacency, and package selection matter more than any generic trace-width rule.

What To Optimize In Each Layout Zone

Layout Zone	What To Optimize	Common Mistake	Related Tool
Driver to gate pin	Shortest practical path with local series resistor at the MOSFET gate	Long detour around the switch node or resistor placed back at the driver	Trace Width + FR4 stackup
Gate return / source reference	Dedicated low-inductance return adjacent to the gate drive path	Using the noisy power source copper as the only gate-return reference	FR4 + system layout review
Bootstrap loop	Capacitor and diode placed directly at driver pins	Long bootstrap feed loop crossing the switch node field	FR4 + layout review
Layer transition	Gate and return move layers together with short via pair or small cluster	One trace changing layers while the return path stays remote	Via Current Calculator
Power stage context	Short DC-link, compact half-bridge, quiet current-sense reference	MCU-first placement that leaves the driver far from the MOSFETs	Motor driver copper guide

Practical Workflow For Gate Driver PCB Layout

Step	Action	Why It Matters	Internal Resource
1. Size the power path separately	Calculate DC bus, phase current, bootstrap supply feed, and any driver supply copper before routing the gate loop.	Power copper, gate copper, and sense copper do different jobs. Mixing them into one width rule produces bad layouts.	Trace Width Calculator
2. Lock the stackup and placement	Keep the driver, MOSFETs, bootstrap capacitor, and local decoupling inside one compact switching cell on the real FR4 stackup.	Once placement is wrong, gate width tweaks rarely recover the ringing or EMI penalty.	FR4 Trace Calculator
3. Check vertical transitions	If the gate loop or source return changes layers, verify the via count and avoid isolated single-via transitions.	A wide top-layer trace can still fail if the loop pinches through one small via.	Via Current Calculator
4. Review the whole motor or power stage	Validate shunt placement, switch-node containment, current loops, and connector escape together with the driver routing.	Gate layout succeeds only when the surrounding power stage is also quiet and physically compact.	Motor Driver Copper Guide

Gate Driver Layout Checklist

+Place the gate driver as close to the MOSFET pair as the package and creepage rules allow.
+Put each gate resistor at the MOSFET gate pin so it damps the real loop instead of a remote branch.
+Route gate and return together; do not let the return wander through high-current source copper.
+Keep the bootstrap capacitor, driver VDD decoupler, and driver ground pin tightly clustered.
+Minimize switch-node copper under or beside sensitive gate and current-sense traces.
+If the design is a motor inverter or robotics board, review current shunt and phase-node placement together with the gate loop.

When To Escalate Beyond Rule-Of-Thumb Layout

Escalate beyond default 10 to 20 mil gate traces when the power stage uses very fast edges, the driver must cross layers, the source lead carries large commutation current, or the board is failing EMI or false-turn-on checks. In those cases, package choice, Kelvin-source routing, and the surrounding half-bridge geometry matter more than generic width rules.

If the design is part of a traction, robotics, or inverter board, also review the surrounding stage with the robotics control PCB guideand the automotive PCB calculatorso the driver layout matches the thermal and current environment it actually lives in.

Design The Gate Loop Before You Polish The Width

A compact driver-to-gate-to-source loop with sane placement usually outperforms a wider but longer route. Use width as a finishing variable after placement, return path, and power-stage containment are already defensible.

Open Trace Width Calculator Check Via Bottlenecks

MOSFET Gate Driver PCB Layout FAQ

What trace width should I start with for a MOSFET gate driver PCB layout?

A practical starting range is about 10 to 20 mil for short gate traces on typical FR4 power boards, but width is secondary to keeping the driver close, the loop compact, and the return path well controlled. A wider trace does not fix a long or badly referenced gate loop.

Should the gate resistor be placed near the driver or near the MOSFET?

Place it near the MOSFET gate. That lets the resistor damp the actual parasitic inductance between the resistor and gate pin. When the resistor sits back at the driver, the remaining trace can still ring aggressively.

Do vias matter on a gate-driver layout even though the gate current is brief?

Yes. The issue is not average current heating but parasitic inductance. Extra vias in the gate loop can worsen overshoot, slow the effective edge seen at the gate, and increase sensitivity to switching noise.

What usually causes MOSFET false turn-on in a half-bridge layout?

The common causes are shared source inductance, poor gate-return referencing, excessive coupling from the switch node into the gate loop, and an overly long path between the driver, resistor, and gate pin.