Memory Interface

DDR4/DDR5 Routing Calculator

DDR4 | DDR5 | LPDDR4/5

Calculate trace width and impedance for DDR memory interfaces. Get the right routing parameters for data, address, command, and clock signals to ensure reliable high-speed memory operation.

DDR Impedance Requirements

Standard	Data Rate	Single-Ended Z	Differential Z
DDR4-2400	2400 MT/s	40Ω	80Ω
DDR4-3200	3200 MT/s	40Ω	80Ω
DDR5-4800	4800 MT/s	40Ω	80Ω
DDR5-6400	6400 MT/s	40Ω	80Ω

DDR Signal Groups & Requirements

Data Signals (DQ/DQS)

• DQ: 40Ω single-ended
• DQS/DQS#: 80Ω differential pair
• Length match DQ to DQS within byte lane
• Typical tolerance: ±25 mils within group
• Route as tight groups by byte lane

Address/Command (ADDR/CMD)

• Address: 40Ω single-ended
• Command: 40Ω single-ended
• Length match to clock
• Typical tolerance: ±50 mils to clock
• T-topology or fly-by routing

Clock (CK/CK#)

• CK/CK#: 80Ω differential pair
• Reference signal for ADDR/CMD
• Route with matched lengths
• Keep away from noisy signals
• Consider termination strategy

Control Signals

• CS#, CKE, ODT: 40Ω single-ended
• Reset#: Standard GPIO
• Less critical timing requirements
• Match to clock group
• Standard routing rules apply

DDR PCB Design Guidelines

📏

Length Matching

DDR requires precise length matching. DQ-to-DQS within ±25 mils, ADDR/CMD to CK within ±50 mils. Use serpentines for length tuning.

🔀

Fly-By Topology

DDR4/5 uses fly-by topology for ADDR/CMD/CLK. Signals visit each DIMM/chip in sequence. Write leveling compensates for timing skew.

⚡

Termination

DDR uses on-die termination (ODT). External termination may be needed for clock signals. Follow memory vendor guidelines for your specific configuration.

Typical DDR4 Trace Dimensions

Data Signals (40Ω SE)

Target Impedance40Ω ±10%

Trace Width (4L)~5-6 mil

Spacing≥3x width

Length Match±25 mil to DQS

Clock/DQS Signals (80Ω Diff)

Target Impedance80Ω Diff

Trace Width (4L)~4-5 mil

Pair Spacing~5-6 mil

Intra-pair Match±5 mil

* Values vary by stackup. Always verify with your actual PCB stack and memory vendor guidelines.

Calculate Your DDR Trace Dimensions

Use our free impedance calculator to determine exact trace width for your DDR design. Enter your stackup parameters for accurate 40Ω single-ended and 80Ω differential calculations.

Impedance Calculator Trace Width Calculator

DDR Design FAQ

What impedance for DDR4?

DDR4 typically uses 40Ω single-ended for data/address signals and 80Ω differential for clock and strobe pairs.

How tight should length matching be?

DQ to DQS: ±25 mils within byte lane. ADDR/CMD to CLK: ±50 mils. Intra-pair differential: ±5 mils.

What's fly-by topology?

DDR4/5 routes clock and address signals to each memory chip in sequence (not parallel). Write leveling compensates for the resulting timing skew.

Do I need special PCB materials for DDR?

Standard FR4 works for most DDR4 designs. DDR5 at higher speeds may benefit from lower-loss materials for longer traces.

Related Tools & Resources

Impedance Calculator

Calculator

Calculate microstrip and stripline impedance

PCIe Impedance Calculator

Standard

PCIe Gen 3/4/5/6 high-speed design

Trace Width Calculator