Power over Ethernet PCB Trace Calculator
802.3af | 802.3at | 802.3bt Power Path Sizing
Use this page to choose a defensible starting point for PoE PCB trace sizing, via planning, and layout review. It separates the controlled-impedance Ethernet channel from the hotter DC power path that actually determines copper width, thermal margin, and reliability on PoE PD and PSE boards.
For PoE boards, do not size power traces from Ethernet impedance rules. Keep data pairs controlled for 100 ohm routing where needed, but size the DC feed path from the PoE interface, bridge, hot-swap section, magnetics center taps, and DC-DC input using current, copper weight, layer, and acceptable temperature rise. On typical 1 oz external copper, short af/at power paths often start around 15 to 25 mil, while 802.3bt power stages commonly justify 30 to 60 mil or copper pours plus via arrays.
Key Takeaways
- •Separate the PoE problem into two channels: 100 ohm Ethernet data pairs and higher-current DC power distribution after the magnetics and rectification path.
- •The most common PoE board mistake is undersizing short but hot sections around bridge rectifiers, hot-swap FETs, TVS devices, and DC-DC input copper.
- •802.3bt designs usually need wider copper, more thermal vias, and explicit return-path planning even when the board is physically small.
- •Use the trace width calculator for DC current paths, the Ethernet and impedance calculators for data pairs, and the via current calculator for any layer changes in the power path.
Use The Right Calculator For Each PoE Section
The most useful PoE workflow is to size the DC power path with the trace width calculator, validate any layer transitions with the via current calculator, and keep the Ethernet data pairs aligned to the Ethernet routing guide.
Size rectified PoE current paths and downstream rails by current and temperature rise.
Check stitched vias under hot devices and any high-current layer changes.
Review current-level reasoning before you finalize compact PoE front-end layouts.
Practical PoE Copper Starting Matrix
| PoE Profile | Typical Power Target | Where To Focus | 1 oz External Start | Recommendation |
|---|---|---|---|---|
| 802.3af / lower-power PD | Up to ~13 W at the PD | Bridge, bulk cap, PD controller input | 15 to 20 mil on 1 oz | Usually manageable on 1 oz copper if the path is short and the converter is efficient. |
| 802.3at Type 2 | Up to ~25.5 W at the PD | Input current path and converter hot spots | 20 to 30 mil on 1 oz | Check copper neck-downs near the bridge, inrush FET, current sense, and connector escape. |
| 802.3bt Type 3 | Up to ~51 W at the PD | Four-pair input path, thermal spreading, vias | 30 to 45 mil on 1 oz | Move early to pours or 2 oz copper if the board is compact or airflow is weak. |
| 802.3bt Type 4 | Up to ~71 W at the PD | All high-current copper and DC-DC launch region | 45 to 60 mil or copper pours | Treat the front end like a thermal design problem, not only a current-capacity calculation. |
These are conservative starting points for short external-copper sections, not final released dimensions. Validate with actual current, copper weight, path length, and acceptable temperature rise.
What To Calculate On A PoE Board
| Board Segment | Electrical Goal | Primary Calculator | Default Approach | Common Mistake |
|---|---|---|---|---|
| PHY to magnetics | 100 ohm differential Ethernet channel | Ethernet / differential impedance | Tight pair routing over a clean reference plane | Widening pair traces for current instead of keeping the channel controlled |
| Magnetics center tap to bridge / PD front end | Low-loss DC current path with low heating | Trace width + current capacity | Short, wide copper and compact hot path | Leaving narrow escapes around bridge, TVS, or inrush components |
| Bridge / hot-swap / bulk capacitor loop | Current handling and thermal spreading | Trace width + via current | Wide copper, pours, multiple vias, minimal loop area | Treating this loop like ordinary signal routing |
| Converter output rails | Board-level current capacity and drop control | Trace width + thermal relief as needed | Size by load current, copper, and regulator placement | Optimizing only the PoE input path while ignoring downstream copper loss |
Recommended PoE Design Workflow
1. Lock the PoE topology
Identify whether the board is a PD, PSE, midspan, or isolated daughtercard and map every current-carrying segment.
The hottest copper is often between the RJ45/magnetics, bridge, and converter input rather than on the long power rails.
2. Size DC copper first
Use the main trace width calculator for the rectified input path, converter feed, and any downstream rails.
PoE power distribution should be sized from current and temperature rise, not from Ethernet pair geometry.
3. Validate vertical current paths
Check vias under hot-swap FETs, controllers, and converter stages, especially when heat or current must change layers.
A narrow via chain can become the actual bottleneck even if the visible top-layer trace looks generous.
4. Keep data and safety rules intact
Confirm the Ethernet data pairs, creepage, and stackup assumptions separately from the power path.
PoE board success depends on both controlled data routing and power-stage reliability.
PoE Layout Checklist
- •Keep the PHY-to-magnetics differential pairs short, symmetric, and referenced to a continuous plane.
- •Use wider copper or pours immediately after the PoE power extraction path instead of carrying DC current through thin Ethernet-style traces.
- •Inspect every neck-down at pads, test points, TVS parts, bridges, and hot-swap FETs because that is where PoE heating concentrates.
- •Add via arrays wherever the power path changes layers or needs thermal spreading into an internal or backside copper region.
- •Check creepage and clearance around the cable entry, primary protection network, and any isolated converter section.
- •Review the actual fabrication stackup before locking any controlled-impedance data pair dimensions.
Most Relevant Follow-Up Pages
For 100 ohm pair routing from PHY to magnetics, use the Ethernet Trace Calculator.
For laminate assumptions and stackup context, verify the FR4 Trace Calculator.
For higher-energy interface spacing and protection review, check the Clearance & Creepage Calculator.
If your converter and connector region must change layers repeatedly, confirm the bottlenecks with the Via Current Calculator.
Power over Ethernet PCB FAQ
Do PoE PCB traces use the same width as Ethernet differential pairs?
No. The Ethernet data pairs still follow controlled-impedance routing rules, typically around a 100 ohm differential target. The extracted PoE power path after the magnetics and rectification section must be sized from current, copper thickness, layer, path length, and allowed temperature rise.
When should I move from narrow traces to copper pours on a PoE board?
Copper pours become attractive as soon as the rectified input path, hot-swap section, or converter input starts carrying higher PoE loads, especially for 802.3bt designs. If the layout is compact, ambient temperature is high, or the current path changes layers, pours and via stitching usually give a better thermal margin than simply choosing one wider trace number.
What is the main calculation mistake on PoE PCBs?
Designers often verify the Ethernet pairs but forget to calculate the short DC segments around the bridge rectifier, TVS, bulk capacitor, and controller input. Those sections may be electrically short, yet they can run hottest because the full PoE current passes through them.
Do I need to check vias on a PoE PD board?
Yes. Any current path that changes layers should be checked with the via current calculator. This matters for thermal spreading under power devices, stitching into ground or power pours, and carrying front-end PoE current into a lower-layer converter region.
Related Tools & Resources
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