0.3mm Via Current Calculator
10 Vias | Standard Via | IPC-2221
For 0.3mm (12 mil) via with 25µm plating and 10 via(s):
(1.90A per via)
Via Parameters
MOD: VIA_CUR_V1Capacity Check
1 vias × --- A each
Understanding 0.3mm Via Current Capacity
A 0.3mm (12 mil) plated through hole (PTH) via with standard 25µm copper plating can carry approximately 1.90A per via based on the IPC-2221 standard. When using 10 parallel via(s), the total current capacity increases to 19.02A, making this configuration suitable for high-current power applications.
Key Parameters for 0.3mm Via
- Hole Diameter: 0.3mm (12 mil) - standard via category
- Plating Thickness: 25µm (standard electroplated copper)
- Board Thickness: 1.6mm (via barrel length)
- Temperature Rise: 10°C (IPC-2221 conservative guideline)
- Cross-Section Area: 25,525 µm² per via
- Resistance: 1.102 mΩ per via
Why Use 10 Parallel Via(s)?
Using 10 parallel 0.3mm vias divides the total current load, reducing thermal stress on each individual via and providing redundancy. With 10 vias, the total resistance drops to 0.110 mΩ (compared to 1.102 mΩ for a single via), resulting in lower voltage drop of 2.10 mV at maximum load.
IPC-2221 Via Current Formula
The IPC-2221 standard calculates via current capacity using the copper annulus cross-sectional area (the ring of copper plating on the via barrel wall). The formula I = k × ΔT^b × A^c determines the current capacity based on the copper area and allowable temperature rise. For a 0.3mm via with 25µm plating, the effective copper area is 25,525 µm², yielding 1.90A capacity per via.
Typical Applications for 0.3mm Via with 19.02A Capacity
Frequently Asked Questions
Can I use fewer than 10 via(s) for 19.02A?
Reducing the number of vias will increase the temperature rise beyond 10°C for the same current. This may be acceptable for some applications, but exceeding 20-30°C rise can affect solder joint reliability and nearby component performance.
Should I use filled or hollow vias for 0.3mm?
For standard vias like 0.3mm, hollow vias with multiple parallel vias (as shown here with 10 vias) are typically more cost-effective than filled vias. Filled vias provide better thermal performance but at higher manufacturing cost.
What spacing should I use between 10 parallel vias?
For 0.3mm vias, a center-to-center spacing of 0.75mm to 0.90mm is recommended. This allows adequate copper pad annular ring and ensures proper current distribution while maintaining manufacturing yield.
Related Via Current Calculations
Complete Your PCB Design
After calculating via current for 0.3mm with 10 via(s), use our other free tools to complete your PCB design. Calculate trace widths for power traces, or analyze impedance for high-speed signals.