High-Speed Impedance: USB, HDMI, PCIe
Every high-speed interface—USB, HDMI, PCIe, DDR—has specific impedance requirements. Get them wrong, and you'll face signal integrity issues, failed compliance testing, or devices that simply don't work. This guide is your complete reference for impedance requirements across all common high-speed interfaces.
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USB Impedance Requirements
USB is everywhere, but each generation has different impedance and routing requirements. All USB versions use differential signaling with 90Ω differential impedance.
| USB Version | Data Rate | Diff. Impedance | Single-Ended | Length Matching |
|---|---|---|---|---|
| USB 2.0 FS | 12 Mbps | 90Ω ±10% | 45Ω | ±150 mil |
| USB 2.0 HS | 480 Mbps | 90Ω ±10% | 45Ω | ±50 mil |
| USB 3.0 (3.2 Gen1) | 5 Gbps | 90Ω ±10% | 45Ω | ±5 mil |
| USB 3.1 (3.2 Gen2) | 10 Gbps | 90Ω ±10% | 45Ω | ±5 mil |
| USB 3.2 Gen2×2 | 20 Gbps | 90Ω ±7% | 42.5Ω | ±3 mil |
| USB4 | 40/80 Gbps | 85Ω ±10% | 42.5Ω | ±2 mil |
USB 3.0+ Routing Tips:
- Keep TX and RX pairs separated by ≥20 mil
- Use ground via stitching between pairs
- Avoid layer transitions if possible
- Match lengths within each differential pair
HDMI Impedance Requirements
HDMI uses TMDS (Transition Minimized Differential Signaling) for data channels and a separate clock. The impedance requirements tighten significantly for HDMI 2.1.
| HDMI Version | Max Data Rate | Diff. Impedance | Max Trace Length |
|---|---|---|---|
| HDMI 1.4 | 10.2 Gbps | 100Ω ±15% | 8 inches |
| HDMI 2.0 | 18 Gbps | 100Ω ±10% | 6 inches |
| HDMI 2.1 | 48 Gbps | 100Ω ±10% | 4 inches |
HDMI Routing Guidelines
- TMDS pairs: Route as tightly coupled differential pairs
- Clock: Match clock to data pair lengths within ±50 mil
- DDC (I²C): Can be routed as standard traces, not impedance-controlled
- CEC: Single-ended, not critical for routing
- HPD: Single-ended, not critical for routing
PCI Express (PCIe) Impedance Requirements
PCIe gets faster with each generation, and impedance requirements get tighter. Gen4 and beyond require careful attention to signal integrity.
| PCIe Gen | Data Rate | Diff. Impedance | Insertion Loss |
|---|---|---|---|
| PCIe 1.0 | 2.5 GT/s | 85Ω ±15% | <6 dB |
| PCIe 2.0 | 5 GT/s | 85Ω ±15% | <8 dB |
| PCIe 3.0 | 8 GT/s | 85Ω ±10% | <10 dB |
| PCIe 4.0 | 16 GT/s | 85Ω ±10% | <14 dB |
| PCIe 5.0 | 32 GT/s | 85Ω ±7% | <20 dB |
| PCIe 6.0 | 64 GT/s | 85Ω ±5% | <28 dB |
PCIe Gen4+ Critical Requirements:
- Use stripline routing for all high-speed lanes
- Minimize via transitions (each via adds ~0.5 dB loss)
- Control impedance at via transitions
- Consider back-drilling for stub reduction
- Use low-loss dielectric (Dk < 3.5) for Gen5+
DDR Memory Impedance Requirements
DDR memory uses a combination of single-ended and differential signals. The data/address lines are single-ended, while the clock and strobes are differential.
| DDR Gen | Data Rate | Signal Z₀ | Clock Zdiff |
|---|---|---|---|
| DDR3 | 800-2133 MT/s | 40Ω ±10% | 80Ω ±10% |
| DDR4 | 1600-3200 MT/s | 40Ω ±10% | 80Ω ±10% |
| DDR5 | 4800-8400 MT/s | 40Ω ±7% | 80Ω ±7% |
| LPDDR4 | 3200-4266 MT/s | 40-50Ω | 80-100Ω |
| LPDDR5 | 6400-8533 MT/s | 40Ω ±5% | 80Ω ±5% |
DDR Length Matching Groups
DDR routing uses byte-lane matching, not global matching. Each group has different requirements:
| Signal Group | Match Within Group | Match to Clock |
|---|---|---|
| DQ[7:0] + DQS0 | ±10 mil | N/A (DQS is the reference) |
| Address/Command | ±25 mil | ±100 mil to CLK |
| Clock (CK/CK#) | ±5 mil (pair) | Reference for CMD/ADDR |
| Control (CS#, ODT) | ±25 mil | ±100 mil to CLK |
Ethernet Impedance Requirements
Ethernet signaling has evolved significantly, with 10GBASE-T and beyond requiring precise impedance control.
| Standard | Data Rate | Impedance | Notes |
|---|---|---|---|
| 10/100BASE-TX | 10/100 Mbps | 100Ω ±15% | Forgiving |
| 1000BASE-T | 1 Gbps | 100Ω ±10% | Standard routing |
| 2.5GBASE-T | 2.5 Gbps | 100Ω ±10% | Use magnetics |
| 5GBASE-T | 5 Gbps | 100Ω ±10% | Short traces |
| 10GBASE-T | 10 Gbps | 100Ω ±5% | PHY to magnetics <1" |
Note: The traces between the PHY and magnetics transformer are the critical high-speed section. The cable-side impedance is handled by the magnetics.
SATA and SAS Impedance
| Interface | Data Rate | Diff. Impedance | Max Length |
|---|---|---|---|
| SATA I | 1.5 Gbps | 100Ω ±10% | 8" |
| SATA II | 3 Gbps | 100Ω ±10% | 6" |
| SATA III | 6 Gbps | 100Ω ±7% | 4" |
| SAS-1 | 3 Gbps | 100Ω ±10% | 10" |
| SAS-2 | 6 Gbps | 100Ω ±7% | 8" |
| SAS-3 | 12 Gbps | 100Ω ±5% | 6" |
Display Interfaces (DisplayPort, MIPI)
| Interface | Data Rate | Impedance | Type |
|---|---|---|---|
| DisplayPort 1.4 | 8.1 Gbps/lane | 100Ω diff | Differential |
| DisplayPort 2.0 | 20 Gbps/lane | 100Ω ±10% | Differential |
| MIPI DSI | 1.5 Gbps/lane | 100Ω ±10% | Differential |
| MIPI CSI-2 | 2.5 Gbps/lane | 100Ω ±10% | Differential |
| LVDS | 655 Mbps | 100Ω ±10% | Differential |
| eDP | 8.1 Gbps/lane | 100Ω ±10% | Differential |
Quick Reference: All Interfaces
| Interface | Diff Z | SE Z | Tolerance |
|---|---|---|---|
| USB 2.0/3.x | 90Ω | 45Ω | ±10% |
| USB4 | 85Ω | 42.5Ω | ±10% |
| HDMI | 100Ω | 50Ω | ±10% |
| PCIe | 85Ω | 42.5Ω | ±5-15% |
| DDR | 80Ω | 40Ω | ±5-10% |
| Ethernet | 100Ω | 50Ω | ±5-10% |
| SATA | 100Ω | 50Ω | ±5-10% |
| DisplayPort | 100Ω | 50Ω | ±10% |
| MIPI | 100Ω | 50Ω | ±10% |
General High-Speed Design Guidelines
1. Reference Plane Integrity
Every high-speed trace needs a continuous reference plane. Splits, voids, and gaps in the reference plane cause impedance discontinuities and return path problems.
2. Via Transitions
Each layer transition adds capacitance and inductance. Minimize transitions for high-speed signals. When transitions are needed, use ground vias nearby. See our Signal Via Guide.
3. Differential Pair Coupling
Keep differential pairs tightly coupled throughout their length. Maintain consistent spacing. Avoid routing between the traces of a pair.
4. Length Matching
Use serpentine routing for length matching, but keep serpentines gradual (avoid sharp turns). Place serpentines near the source, not the destination.
Calculate Your Trace Dimensions
Now that you know your target impedance, use our calculators to determine the right trace dimensions:
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