MIPI CSI PCB Routing Calculator
CSI-2 | D-PHY | Camera FPC Routing
Use this MIPI CSI-2 routing resource to choose defensible starting rules for camera differential pairs, connector launches, length matching, ESD placement, and stackup checks before committing the layout.
For most MIPI CSI-2 camera routes, start with a short 100 ohm differential D-PHY pair geometry from your fabricator stackup, keep clock and data lanes over a continuous reference plane, match lane lengths to the image sensor or SoC vendor guide, and avoid uncontrolled neck-downs at FPC connectors, ESD arrays, and layer changes.
Key Takeaways
- •Treat MIPI CSI as a controlled-impedance channel once the route leaves a compact module area or crosses an FPC connector.
- •A practical first-pass target is 100 ohm differential for D-PHY high-speed lanes, but the final width and spacing must come from the actual board or flex stackup.
- •Connector breakout, ESD placement, and return-path continuity usually create more risk than the straight trace segment.
- •Keep all CSI lanes short, symmetric, and referenced; use vendor-specific length matching limits when they are tighter than generic layout rules.
Start With The Channel
MIPI CSI routing is a stackup and discontinuity problem. Use the differential impedance calculator for D-PHY lanes, the impedance calculator for single-ended transitions, and the flex PCB calculator when the camera path moves onto an FPC.
MIPI CSI Routing Decision Matrix
| Design Scenario | Routing Target | Recommended Action | Main Risk |
|---|---|---|---|
| Same-board image sensor | Short 100 ohm differential D-PHY routes | Use compact pair routing and minimize layer changes. | Sensor escape fanout and local discontinuities. |
| Board-to-FPC camera module | Continuous pair geometry through connector launch | Model PCB plus flex stackups separately and keep connector pinout symmetric. | FPC launch, ESD stub, and ground pin placement. |
| Wearable or compact camera board | Shortest manufacturable route with stable return path | Prefer adjacent ground, controlled bends, and minimal via count. | Dense routing forcing plane splits or long detours. |
| Multi-camera processor board | Repeatable lane geometry per camera port | Document constraints per connector and route matched groups independently. | Lane swaps, mixed connector lengths, and inconsistent stackup zones. |
Practical Layout Workflow
1. Lock the stackup before routing
Get dielectric height, copper thickness, soldermask assumptions, and flex construction from the fabricator.
Use FR4 Trace Calculator2. Calculate D-PHY lane geometry
Use the actual reference-plane distance to choose trace width and spacing for the differential pair target.
Use Differential Impedance Calculator3. Check single-ended side effects
Review any lane escape, neck-down, or transition that temporarily behaves as a single-ended impedance section.
Use Impedance Calculator4. Size support copper separately
Camera rails, IR LEDs, autofocus drivers, and module power are current problems, not D-PHY routing problems.
Use Trace Width CalculatorConnector And ESD Checklist
Camera links often fail at the FPC launch or protection network, not in the middle of the route. Use this checklist before sending the layout to fabrication.
- •Keep clock and data pairs on one layer where possible; if a layer change is required, transition both traces together.
- •Place ESD arrays close to the connector without adding long side stubs to the high-speed lanes.
- •Use adjacent ground pins or ground stitching near FPC connector launches when the connector pattern allows it.
- •Avoid routing MIPI lanes across plane voids, split references, dense via fields, or noisy switching regulator areas.
- •Keep pair spacing and width consistent through the route; make unavoidable neck-downs short and symmetric.
- •Capture the final impedance and length-matching assumptions in layout notes for fabrication and review.
When To Escalate The Review
Escalate from rule-of-thumb routing to explicit impedance review when the design uses long FPC cables, multiple cameras, small-pitch connectors, rigid-flex transitions, or tight EMC requirements.
For embedded vision systems in drones, wearables, and instruments, also review the related wearable PCB, drone flight controller, and test and measurement PCB resources.
MIPI CSI vs USB Differential Routing
| Factor | MIPI CSI | USB | Layout Decision |
|---|---|---|---|
| Primary target | Short controlled D-PHY lanes, commonly 100 ohm differential | 90 ohm differential cable and connector ecosystem | Do not reuse USB geometry blindly; calculate MIPI from the camera board stackup. |
| Route length pressure | Usually very short and connector-dominated | Often longer board paths with external cable transitions | Spend review time on connector launches, ESD stubs, and lane matching. |
| Common board types | Camera modules, wearables, drones, embedded vision | General host/device interconnects | Check flex and rigid-flex constraints earlier for MIPI designs. |
| Failure pattern | Intermittent camera bring-up, lane training errors, image corruption | Enumeration failures, eye margin loss, EMI issues | Preserve clean return paths and avoid asymmetric discontinuities on every lane. |
For USB-specific rules, use the USB trace width calculator.
Calculate The MIPI Pair Before Routing
Enter the real dielectric height, copper thickness, and target spacing before locking camera connector placement. MIPI routing is easiest to fix before dense fanout and FPC mechanical constraints are frozen.
MIPI CSI PCB Routing FAQ
What impedance should I use for MIPI CSI-2 D-PHY lanes?
A common starting point is 100 ohm differential impedance for high-speed D-PHY lanes. Confirm the exact target, tolerance, and any single-ended requirements in the image sensor, camera module, or SoC vendor layout guide.
Can I copy USB differential pair dimensions for MIPI CSI?
No. USB and MIPI often use different targets, connectors, stackups, and route lengths. Recalculate the trace width and spacing from the actual PCB or flex stackup instead of copying a USB rule.
How important is length matching for MIPI camera lanes?
It matters, but the exact limit is implementation-specific. Match each differential pair tightly, keep lanes in a camera port reasonably balanced, and follow the SoC or sensor vendor guide when it gives numeric skew limits.
Do MIPI CSI traces need to be routed over ground?
Yes. Route the lanes over a continuous reference plane whenever possible. Plane gaps, connector voids, and noisy return paths can cause more trouble than a small error in nominal trace width.
Should ESD protection go before or after the FPC connector?
Place ESD protection close to the external or exposed connector path, but keep the high-speed connection short and symmetric. The best placement depends on the mechanical connector, ground strategy, and module exposure.
Related Tools & Resources
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