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Engineering GuideDecember 12, 202411 min read

Via Sizing: How Many Vias Needed?

Quick Answer

Calculate the exact number of vias needed for your PCB. Engineering formulas for current requirements with practical examples.

"How many vias do I need?" It is one of the most common questions in PCB design, and one that is surprisingly tricky to answer. Too few vias and you risk thermal failures or voltage drop issues. Too many and you waste board space and increase cost.
This guide gives you the formulas, tables, and rules of thumb to calculate exactly how many vias you need, whether for power delivery, thermal management, or ground stitching. No more guessing.

Via Basics: Anatomy of a Via

Before calculating via count, it helps to understand what determines a via's current and thermal capacity.
Via Anatomy and Parameters
ParameterDescriptionTypical Values
Drill DiameterHole size before plating8-20 mil
Finished DiameterHole size after plating6-18 mil
Plating ThicknessCopper on barrel wall0.8-1.5 mil
Pad DiameterCopper ring around holeDrill + 8-16 mil
Aspect RatioBoard thickness / drill size6:1 to 12:1
Key Insight: Current flows through the copper plating on the via barrel, not through the center. A larger via has more plating surface area and therefore higher current capacity.

Single Via Current Capacity

The current capacity of a single via depends on plating thickness, drill size, and allowable temperature rise.
Single Via Current Capacity (1 mil plating, 10°C rise)
Drill SizePlating AreaCurrent (10°C)Current (20°C)
6 mil0.47 mil²0.4 A0.5 A
8 mil0.63 mil²0.5 A0.7 A
10 mil0.78 mil²0.7 A0.9 A
12 mil0.94 mil²0.9 A1.2 A
15 mil1.18 mil²1.2 A1.5 A
20 mil1.57 mil²1.6 A2.0 A
These values assume standard plating thickness. For thicker plating such as 1.5 mil IPC Class 3, increase capacity by about 30%.

How to Calculate Via Count

There are two practical ways to size a via array depending on whether you care most about current delivery or matching the connected copper geometry.

Via Count = (Required Current ÷ Single Via Capacity) × Safety Factor

Method 1: Current-Based Calculation

For power delivery, divide the required current by single-via capacity and add a safety factor.

Method 2: Trace Width Matching

Match the total via cross-section to the trace cross-section so the transition does not become a bottleneck.
  • Use a safety factor of 1.25 for standard applications.
  • Use a safety factor of 1.5 for high-reliability or thermally stressed designs.
Via Count to Match Trace Width (10 mil vias, 1oz copper)
Trace WidthTrace AreaVias Needed
20 mil27 mil²2-3
50 mil68 mil²4-5
100 mil137 mil²7-8
200 mil274 mil²14-16
Example: A 5A rail crossing layers through 10 mil vias with 0.7A single-via capacity needs about 9 vias after applying a 1.25 safety factor.
The cross-section method can also be useful: Via Count = (Trace Width × Trace Thickness) ÷ Via Plating Area.

Quick Reference: Via Count by Current

For fast estimates, this table assumes 10 mil drill vias with 1 mil plating and 10°C temperature rise.
Recommended Via Count by Current (10 mil vias)
CurrentMin ViasRecommendedHigh-Rel
0.5 A122
1 A22-33
2 A345
3 A568
5 A89-1012
10 A1518-2025
15 A2225-2835
20 A293545
Need exact numbers? Use the Via Current Calculator to size arrays from your actual plating, board thickness, and temperature-rise targets.

Via Sizing by Application

Different via arrays are optimized for different jobs. A power transition array is not the same as a thermal pad array or a stitching fence.
Power Via Recommendations
ApplicationTypical CurrentVia SizeVia Count
MCU power100-500 mA10 mil2-4
Motor driver1-5 A12-15 mil6-12
LED driver0.5-2 A10-12 mil3-6
DC-DC output2-10 A12-15 mil8-20
Battery connection5-20 A15-20 mil15-40
Thermal Via Array Recommendations
Power DissipationPad SizeVia SizeVia Count
0.5 W3×3 mm12 mil4-6
1 W4×4 mm12-15 mil9-12
2 W5×5 mm15 mil12-16
5 W8×8 mm15-20 mil25-36
For thermal pad planning, compare these numbers with the Thermal Via vs Signal Via Guide.

Ground Stitching Vias

Ground stitching keeps return paths short and predictable for high-speed signals. Spacing depends on the highest frequency you care about.
Ground Stitching Via Spacing
Max FrequencyWavelength (FR4)Max Via Spacing
100 MHz~1500 mm150 mm (no stitching needed)
500 MHz~300 mm30 mm
1 GHz~150 mm15 mm (600 mil)
2.4 GHz~62 mm6 mm (240 mil)
5 GHz~30 mm3 mm (120 mil)
Rule of Thumb: Space ground stitching vias at λ/20 or less, where λ is the wavelength at the highest signal frequency. This keeps the return path well controlled.

Via Placement Best Practices

1. Power Via Arrays

  • Place vias in a grid pattern under pads or along traces.
  • Use a minimum spacing around 3× via diameter.
  • Distribute current so one via does not become a hot spot.
  • Spread the vias evenly across the copper area.

2. Thermal and Signal Transitions

  • Center thermal vias under the heat source.
  • Use roughly 1.0-1.2 mm pitch for many thermal pads.
  • Place ground vias within 20-30 mil of signal vias.
  • Consider back-drilling or HDI vias for very fast signals.

Via Voltage Drop Calculation

Vias add resistance as well as temperature rise. In low-voltage rails, that resistance can matter almost as much as heating.
Single Via Resistance (62 mil board, 1 mil plating)
Via DrillResistanceV-Drop at 1A
8 mil~0.6 mΩ0.6 mV
10 mil~0.5 mΩ0.5 mV
12 mil~0.4 mΩ0.4 mV
15 mil~0.3 mΩ0.3 mV
For multiple vias in parallel, divide the single-via resistance by the via count. Total path voltage drop includes both traces and vias, so pair these checks with the Trace Width Calculator.

Real-World Examples

Example 1: Motor Driver Power Stage

Design: 12V motor driver, peak current 8A, layer transition from external trace to internal plane.

Via drill: 12 mil → Single via capacity: 0.9A (10°C)
Required vias: 8A ÷ 0.9A = 9 minimum
With 1.25× safety factor: 9 × 1.25 = 12 vias
Arrangement: 3×4 grid at 40 mil pitch under the power pad.

Example 2: Voltage Regulator Thermal Pad

Design: LDO dissipating 1.5W, 5 mm × 5 mm exposed pad, connected to ground plane.

Thermal pad area: 25 mm²
Via diameter: 15 mil (0.4 mm) with 0.8 mm pad
Via pitch: 1.0 mm for strong thermal transfer
Via array: 4×4 = 16 vias
Fill option: plugged or tented to reduce solder wicking.

Example 3: USB 3.0 Signal Transition

Design: USB 3.0 SuperSpeed (5 Gbps) differential-pair layer transition.

Signal via: 8 mil drill for lower capacitance
Ground vias: 2 per signal via, about 25 mil away
Configuration: GND-D+-D--GND
Consider back-drilling to reduce via stub length.

Common Via Sizing Mistakes

Using only one via for high-current connections. A single 10 mil via only carries about 0.7A safely under common assumptions, so power rails usually need several in parallel.
Cramming vias too close together. Overly dense arrays create fabrication risk and poor current sharing. Keep at least 3× via diameter spacing, and 4× is often safer.
Ignoring aspect ratio limits. A tiny via through a thick board can become impossible to plate reliably. Standard fabs are much happier near 8:1 than 17:1.
Forgetting plane connection bottlenecks. A via farm does not help if it feeds into a narrow trace or poor plane neckdown.

Summary: Via Count Formula

This is a good first-pass shortcut for 10 mil vias with 1 mil plating at a 10°C rise.
For accurate results tailored to your design, use the Via Current Calculator. It accounts for via size, plating thickness, board thickness, and temperature rise.

Via Count = (Current ÷ 0.7A) × 1.25

When you need to visualize thermal zones and array placement, 3D mechanical review can also help. Modern 3D modeling workflows are increasingly useful during electronics prototyping.

Related Reading

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Via SizingVia CountCurrent CapacityPCB Design

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