Engineering GuideApril 22, 2026• 10 min read
When to Use Thermal Vias Under Hot Components
Quick Answer
Use thermal vias under hot components when the package includes an exposed pad or concentrated heat source and top-layer copper alone cannot move the heat into larger inner or bottom copper. They are usually worth adding for regulators, power QFNs, LEDs, motor drivers, and compact MOSFET stages above roughly 1W to 2W of local dissipation, but they should be reviewed carefully when solder wicking, via fill cost, isolation spacing, or assembly yield is the bigger constraint.
Key Takeaways
- •Thermal vias are most valuable when heat is trapped in a small pad area, not when the board already has enough top-side copper and airflow.
- •Exposed-pad packages, LED thermal pads, DC/DC controllers, linear regulators, and compact MOSFET stages are the most common cases where a via array pays off.
- •Open vias directly in solderable pads can hurt assembly yield; tented, plugged, or filled vias are often the safer production choice.
- •A thermal-via array has to be sized together with copper area, bottom-side spreading, and the actual heat path into chassis or airflow.
Use thermal vias under hot components when a small package pad is trying to dump more heat than the top layer can spread by itself. In practice, they are most useful under exposed-pad regulators, QFNs, LEDs, MOSFETs, and compact power modules where the local heat density is high and you have meaningful copper on inner or bottom layers to receive that heat. If the top side already has ample copper, airflow, or a direct heatsink path, more vias may add complexity without much benefit.
The fastest engineering workflow is to check three items together: local dissipation, available copper area, and assembly method. Start with the Trace Width Calculator for current paths, the Via Current Calculator for shared via bottlenecks, and the Current Capacity Calculator when the same copper path also carries meaningful current.
Use Thermal Vias When Heat Is Concentrated Into a Small Pad
The key question is not whether the component runs warm. The real question is whether the heat is trapped in a small footprint with too little top-layer spreading area. A large TO-220 with a chassis mount may not need vias under the pad at all, while a tiny QFN buck regulator can benefit immediately because most of its heat exits through one exposed thermal paddle.
Thermal vias are most effective when they connect that concentrated heat source into copper that actually helps: an internal plane, a bottom copper flood, a metal-backed region, or a secondary heatsink interface. If the receiving layers are chopped up by split planes, clearance constraints, or dense routing, then the via field has nowhere useful to send the heat.
This is why the decision belongs in the same review as thermal-via versus signal-via planning and internal versus external layer strategy. A via array is not a magic fix. It is part of a larger heat-spreading path.
Direct recommendation: Add thermal vias when the package has an exposed pad and the product would otherwise rely on a small top copper island to remove more than roughly 1W to 2W of local heat.
Decision Matrix: When Thermal Vias Are Worth It
| Component situation | Use thermal vias? | Good starting point | Main caution |
|---|---|---|---|
| QFN or DFN regulator with exposed pad, about 1W to 3W local loss | Usually yes | 4-9 vias under the pad tied to inner and bottom copper | Prevent solder wicking with plugged, filled, or carefully tented vias |
| High-brightness LED on FR-4 board | Usually yes | Dense via field under thermal slug into back copper or metal interface | The bottom side still needs real spreading area or chassis coupling |
| Power MOSFET stage with strong top and bottom pours | Often yes | Use vias near the thermal pad and current loop, not only in one corner | Do not create current bottlenecks or long neck-downs around the array |
| Linear regulator dissipating less than about 0.5W with open airflow | Often not necessary | Try larger top copper first | Extra vias may add cost with little measurable gain |
| Module already bonded to heatsink or chassis from top side | Maybe | Use vias only if the PCB is still part of the intended heat path | Do not assume more vias help when the dominant path is elsewhere |
| Isolation-sensitive or high-voltage pad with tight creepage rules | Case by case | Review safety spacing before adding any array | Thermal gain does not justify violating clearance or creepage |
This matrix is intentionally practical: a thermal-via array is justified by thermal density and a real downstream heat path, not by habit.
The Best Candidates: Regulators, LEDs, Drivers, and Dense Power Stages
These are also the designs where engineers often need both thermal and electrical review at the same time. The same copper under a MOSFET or regulator pad may be handling heat spreading, current transfer, and return-path control together. That is why the via sizing guide and IPC-2152 temperature-rise examples are useful companion references.
- Buck, boost, and LDO regulators with exposed pads: These packages often route most heat through the center pad, so vias under that pad can reduce junction temperature materially when the board is compact.
- Motor drivers and gate-driver ICs: These devices combine switching loss, conduction loss, and often limited footprint area, making the exposed pad the natural thermal exit.
- High-power LEDs: LED lifetime is strongly tied to junction temperature. If the PCB is part of the thermal chain, vias under the slug are usually standard practice.
- Compact MOSFET and power-stage layouts: When the copper area near the device is constrained by loop-inductance targets, thermal vias can move heat downward without forcing a longer top-side route.
- Power modules on standard FR-4: If the module pad is small relative to dissipation, vias help spread heat into more board area before you jump to heavier copper or an external heatsink.
When Thermal Vias Are the Wrong First Fix
Design teams often jump to thermal vias because they are easy to sketch. But if the thermal path is dominated by poor airflow, a sealed enclosure wall, or an undersized copper neck-down elsewhere, the via array will not solve the real limitation.
"Thermal vias are a strong tool, but only after the board has somewhere useful to send the heat. I would rather see six well-placed vias into solid copper than twenty vias into thermal dead ends."
Adding vias before enlarging easy copper area. If the board still has room for a larger top pour, that may buy thermal margin more cheaply than via-in-pad processing.
Using thermal vias with no receiving copper. A via field that lands in fragmented copper or narrow traces below the part cannot move heat effectively.
Ignoring assembly yield. Open vias in solderable pads can steal solder and tilt QFNs or reduce voiding control.
Using tiny drills beyond the fab comfort zone. An aggressive array only helps if the supplier can build it consistently and at acceptable cost.
Forgetting the real thermal bottleneck. Sometimes the hottest point is the inductor, connector, shunt, or enclosure interface, not the IC pad itself.
Layout Checklist for Thermal Vias Under Hot Components
| Checkpoint | What good looks like | Red flag |
|---|---|---|
| Package heat path | Datasheet shows the exposed pad or slug as the main thermal exit | Thermal vias added even though the package mainly cools elsewhere |
| Receiving copper | Inner or bottom layers provide meaningful copper area under the part | Vias land in cut-up copper with little spreading value |
| Via process | Open, tented, plugged, or filled choice matches assembly risk | No one has confirmed the via finish with the fab and assembler |
| Pitch and drill | Array fits the pad geometry and the supplier's manufacturable drill rules | Array is so dense that annular ring, mask, or yield becomes marginal |
| Current path interaction | Copper around the array still supports current and return flow cleanly | Array forces narrow neck-downs or awkward current detours |
| Thermal validation | Team has a target junction, case, or board temperature margin | Thermal vias added with no measured or estimated goal |
Recommended Starting Rules for Engineers and Buyers
- Read the package thermal guidance first and confirm whether the exposed pad is the primary heat path.
- Estimate local dissipation and ask whether top copper alone can spread it within the allowed temperature rise.
- If not, add an initial array of roughly 4-9 vias on about 0.8 mm to 1.2 mm pitch for many small power pads, then scale from package size and fab rules.
- Decide early whether the pad needs open, tented, plugged, or filled vias based on assembly volume and yield targets.
- Review the same area for current bottlenecks, especially if the part also handles high current.
- Measure one prototype with thermocouples or IR plus electrical load, then adjust the array, copper area, or assembly spec from real data.
- → Trace Width Calculator for copper path sizing
- → Via Current Calculator for shared electrical and thermal vias
- → Thermal Relief Calculator for solderability tradeoffs
- → Via sizing guide for choosing count, drill, and pitch
- → Thermal via vs signal via guide for design intent
For most practical PCB programs, the search intent behind this topic is simple: when does a thermal-via array under the component actually help? The answer is when the package pushes heat into a small pad, the board can spread that heat to other copper, and the assembly method can support the via structure without hurting yield.
Tags
Thermal ViasThermal PadPCB Thermal DesignPower PCBVia Array
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Quick FAQ
At what power level should I consider thermal vias under a component?
A practical starting point is around 1W to 2W of local dissipation in a compact package, especially when the package has an exposed pad and the board cannot spread heat well on the top layer alone. In sealed products or high-ambient designs, the threshold can be lower.
Do thermal vias always reduce component temperature?
No. They help only when they connect the heat source into useful copper area or another cooling path. If the bottom side is crowded, isolated, or thermally blocked, more vias may add cost without a meaningful temperature drop.
Should thermal vias be open, tented, plugged, or filled?
For solderable pads, plugged or filled vias are usually safer because they reduce solder wicking. Open vias can work for prototypes and some non-critical assemblies, but they raise yield risk. Tented vias can help in lighter-duty cases if the fabricator can hold the mask reliably.
How many thermal vias should I start with under a hot pad?
For many QFN regulators and drivers, a first pass is 4 to 9 vias on roughly 0.8 mm to 1.2 mm pitch inside the exposed pad area, then adjust from the package size, drill limits, copper area, and measured thermal margin.
What should a buyer confirm with the PCB supplier before approving thermal vias in pads?
Confirm finished drill size, aspect ratio, via plugging or filling process, planarization, solder-mask capability, and any added cost or lead time. Thermal-via strategy is partly a fabrication decision, not only a layout decision.
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