IPC-2221 / IPC-2152 Compliant
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Stackup Workflow

Controlled Impedance Stackup Calculator Guide

Microstrip | Stripline | Differential Pairs

Choose a manufacturable controlled impedance PCB stackup before routing high-speed traces. This guide connects stackup inputs, impedance targets, copper limits, and fabrication notes into one release-ready workflow.

Controlled Impedance Stackup Decision Matrix

Board PatternBest FitLayer ChoiceStarting GeometryRisk To CheckRelated Page
Simple 4-layer FR4USB 2.0, 1G Ethernet, short LVDSOuter microstrip over L2 ground5 to 7 mil trace with fab-approved dielectric heightDk variation and solder mask can shift impedance; get final values from the board house.FR4 guide
Dense 6-layer digitalUSB 3.x, MIPI CSI, PCIe short runsInner stripline or adjacent reference-plane microstrip4 to 5 mil trace, tighter spacing for differential pairsRouting density can push geometry below economical fabrication limits.Differential calculator
Low-loss high-speedPCIe Gen4+, HDMI 2.x, long SERDESStripline with low-loss dielectric or hybrid stackupUse material-specific Dk and loss tangent from the laminate datasheetLoss budget may dominate over nominal impedance once the route gets long.Rogers guide
Flex or rigid-flexCamera, wearable, sensor, folded interconnectMicrostrip or coplanar style approved by the flex vendorUse polyimide Dk, adhesive thickness, and bend-zone rulesMechanical bend rules can be more restrictive than impedance geometry.Flex calculator

Stackup-To-Fab Workflow

StepActionDesign Review Check
1. Define the signal classList each controlled net by target impedance: 50 ohm single-ended, 85/90/100 ohm differential, or vendor-specific RF target.Do not mix USB, PCIe, Ethernet, MIPI, and RF assumptions into one generic width rule.
2. Choose layer typeSelect microstrip, stripline, or coplanar routing based on access, shielding, via count, and return path continuity.A layer swap changes impedance even when the trace width stays the same.
3. Lock stackup inputsUse actual Dk, dielectric height, finished copper, solder mask, and minimum trace/space from the fabricator.Finished copper is what matters for impedance; base copper alone can be misleading.
4. Calculate and sanity-check geometryRun the impedance calculator, then compare width and spacing against design rules and connector escape constraints.Change stackup if the geometry is too narrow, too wide, or impossible to route consistently.
5. Release controlled-impedance notesDocument target impedance, tolerance, layer, geometry, reference plane, and coupon/test requirements in fabrication notes.Fab notes should specify what must be controlled, not every signal that merely looks high speed.

When To Change The Stackup

  • -The calculated trace is below the fabricator minimum or leaves no margin for etch tolerance.
  • -Differential spacing cannot stay consistent through connectors, vias, or BGA escapes.
  • -High-speed routes become too long for standard FR4 loss, especially on PCIe, HDMI, or long SERDES channels.
  • -Power traces, copper pours, or clearance rules fight the impedance geometry on the same layer.

Protocol-Specific Checks

After the generic stackup looks buildable, validate the exact interface target. Use the USB trace width calculator for 90 ohm USB pairs, the PCIe impedance calculator for 85 ohm high-speed serial links, and the MIPI CSI routing guide for camera FPC transitions.

For power-heavy boards, check whether the same copper weight still satisfies thermal requirements with the IPC-2152 trace width guide before finalizing layer thickness.

Build A Fabricator-Ready Impedance Rule

Choose the target, calculate geometry from the real stackup, then document layer, width, spacing, reference plane, tolerance, and coupon expectations. That makes the impedance requirement testable instead of vague.

Controlled Impedance Stackup FAQ

What is the first input for a controlled impedance stackup calculator?

The first input should be the real fabrication stackup: dielectric height, material Dk, finished copper thickness, solder mask assumptions, and minimum trace/space. Generic board thickness is not enough.

Should I route controlled impedance on outer or inner PCB layers?

Use outer-layer microstrip when access, rework, or fewer vias matter. Use inner-layer stripline when shielding, repeatability, and crosstalk control matter more. The best choice depends on the signal standard and board density.

What tolerance should I specify for controlled impedance?

A +/-10% target is common for many digital interfaces during early design. Tighter tolerances increase fabrication cost and should be confirmed with the board house before layout release.

Can I calculate impedance before choosing a PCB manufacturer?

You can estimate it, but final dimensions should use your intended manufacturer stackup. Two FR4 boards with the same layer count can require different trace widths because dielectric height, resin content, copper plating, and process rules differ.

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