Designing PCB Traces for PoE Current Levels
For most IEEE 802.3af and 802.3at boards, start with 20-30 mil external traces for the main 48V feed, widen the bridge-to-bulk-capacitor path before the long cable-side runs, and treat vias, connector pins, and hot-swap bottlenecks as the real thermal limiters.
Najważniejsze wnioski
- •PoE trace sizing should follow the power path, not every differential Ethernet trace around it.
- •802.3af usually fits on practical 1oz outer-layer traces; 802.3at often wants 25-35 mil trunks or pours; 802.3bt commonly pushes you toward wider pours and heavier via fields.
- •The hottest PoE copper is usually at the RJ45 breakout, bridge rectifier, inrush FET, and DC/DC input neck-downs.
- •Connector ratings, bridge losses, and layer-change bottlenecks should be checked alongside the trace-width calculator.
PoE Current Levels That Matter for Trace Sizing
| PoE level | PSE power | Pair current | Practical PCB starting point |
|---|---|---|---|
| 802.3af Type 1 | 15.4W | ~350mA per pair | 20 mil external trunk is usually comfortable for the main feed. |
| 802.3at Type 2 | 30W | ~600mA per pair | Start around 25-35 mil on the bridge and bulk-cap path. |
| 802.3bt Type 3 | 60W | Up to ~600mA per pair across 4 pairs | Use pours or wide trunks and check every via transition. |
| 802.3bt Type 4 | 90W | Up to ~960mA per pair across 4 pairs | Treat bridge, FET, shunt, and converter input as heavy-copper zones. |
Practical Width Starting Points
- Keep 802.3af power trunks on outer layers when possible; 20 mil is a safe starting point for short runs on 1oz copper.
- For 802.3at, use 25-35 mil on the bridge-to-bulk-capacitor path and avoid narrow test-point branches in the main current loop.
- For 802.3bt front ends, pours usually route better than one oversized trace because current splits across multiple entry points and components.
- Do not forget voltage drop. A thermally acceptable trace can still waste headroom before the hot-swap controller or flyback input.
"On PoE boards, I usually widen the bridge and converter entry before I touch the cable-side pair routing. A 10 mm bottleneck can dominate the whole thermal picture."
Where PoE Boards Usually Overheat First
- Check the RJ45 or magjack breakout first. Pin escapes, center taps, and ESD or surge parts often force short copper bottlenecks.
- Review the bridge rectifier to bulk capacitor segment. That short path carries real DC current and sees diode loss at the same time.
- Inspect the inrush FET, ideal-diode, or hot-swap section. Thermal rise there is often worse than on the longer 48V trunk.
- Count vias across every layer change. The via field should match the copper cross-section feeding it, especially on compact PD boards.
"For 802.3bt, the via array and the bridge section usually deserve the same attention as the trace width number from IPC-2152. If one of them is undersized, the calculator result is not enough."
Release Checklist for Engineers and Buyers
- Size from delivered PoE power and worst-case ambient, not lab-room current only.
- Check bridge, FET, shunt, and connector losses separately from straight-trace ampacity.
- Match the via count to the incoming copper width at every layer transition.
- Review creepage and clearance around the 48-57V front end plus surge parts.
- Share the copper weight, temperature-rise target, and expected power class with your PCB supplier before fabrication.
- → Open the PCB Trace Width Calculator
- → Check PoE layer changes with the Via Current Calculator
- → Review pair geometry with the Ethernet Routing Calculator
"Buyers should ask one simple question: where is the narrowest copper in the powered path after the RJ45? That answer usually predicts whether the first prototype runs cool or arrives with avoidable hot spots."
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Szybkie FAQ
What trace width should I start with for PoE on 1oz copper?
A practical starting point is about 20 mil for 802.3af, 25-35 mil for 802.3at power trunks, and wider pours or 50 mil+ sections for 802.3bt bottlenecks after the bridge, depending on layer, ambient temperature, and allowable rise.
Do PoE data pairs need to be widened for current carrying?
Usually no. Keep the Ethernet pairs routed for signal integrity. Size the DC power path, center-tap feed, bridge, surge path, and DC/DC input for current and heat instead of widening every differential pair segment.
Where do PoE boards usually overheat first?
The common hot spots are RJ45 or magjack pin escapes, bridge rectifiers, inrush FET paths, diode OR-ing, test-point neck-downs, and undersized via arrays between the PoE front end and the converter.
Is 2oz copper necessary for PoE boards?
Not for every design. Many 802.3af and 802.3at products work well on 1oz outer layers. Move toward 2oz when 802.3bt power, high ambient temperature, small board area, or strict voltage-drop margin makes 1oz routing awkward.
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